Low-cost congestion control techniques for Networks-on-Chip based multi-core processors

Date
2016
Authors
Debnath, Monobrata
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Abstract

Rapid innovations in circuit integration technology have successfully integrated billions of transistors on a single chip. The advancement in IC technology has put the challenge of extracting the maximum performance gain from additional resources. In the recent times, computer architects have exhorted many-core design to meet next generation computation demands. Chips, equipped with a large number of cores, bracing dynamic parallelism and modest power usage are proposed to meet future computation needs. Intriguingly, the performance of the many-core architecture greatly relies on the competence of on-chip interconnection network. Networks-on-Chip (NoCs) has emerged as the backbone of many-core architectures. Nevertheless, poor network performance due to congestion could become a major hindrance in the future multi-core designs. In the present research, we investigate the causes of congestion in NoCs and facilitate ways to mitigate the performance threat. In particular, our focus is on providing cost effective congestion management solutions suitable for NoCs.

We introduced a low overhead, deadlock free and holistic approach to manage congestion, especially for Mesh and Dimension Order Routing (DOR) conjunction. The proposed method called as In-Network-Throttling successfully attenuates network congestion without incurring any significant overhead.

To further alleviate congestion, we synergically combined two traffic throttling techniques known as Edge -Throttling and In-Network-Throttling. The Edge-Throttling regulates packet injection locally whereas In-Network-Throttling balances traffic load across the network. The combination is a deadlock free, low-cost alternative to state-of-the-art adaptive routing techniques, yielding better throughput improvements, but at a significantly lower cost.

In our third approach, we developed a fine-grained in-network throttling technique by dynamically selecting the throttling direction. The proposed Multiport-Throttling method considers incoming traffic from all the neighbor routers and performs dynamic throttling based on the congestion status. The current approach shows significant improvement over the two previous methods with negligible hardware increment.

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Keywords
congestion management, Low-Cost, multi-core, network-on-chip, traffic throttling, VC arbitration
Citation
Department
Electrical and Computer Engineering