An Ultra Low Power VLSI Implementation of the 128-Bit AES Algorithm Using a Novel Approach to the ShiftRow Transformation
With the fast growing digital world, security of data has become a critical issue. The security of personal data has become the most important aspect of modern technologies and to tackle this challenge, an age old technique known as cryptography is widely applied. A tremendous amount of work has been done in this realm with great progress over the years. Various cryptographic algorithms such as DES, 3DES, Blowfish, Twofish and AES have been developed over the years to address the security of data. Presently, the most widely used cryptographic algorithm is the Advanced Encryption Standard also called as the AES Algorithm in short. Since the inception of AES, many advancements have been achieved and much work has been done to get better values for the parameters under measurement. However, for most present-day applications, such as portable devices and Internet of Things (IoTs) in which battery power is limited, power efficiency and throughput are of utmost importance. Hence, ultra-low power implementation of the AES algorithm has become important for a range of devices. This thesis focuses on optimizing the power consumption of the 128-bit AES Algorithm.
Various low power VLSI techniques exist and are used widely for the purpose of power optimization of the design and implementation of digital systems. However, that alone is not enough and is not the best way to achieve reduced power consumption. Rather than just applying a low power technique on an existing design, this thesis develops an alternate algorithm and then uses low power techniques on the modified algorithm. This is done by analyzing various layers of the AES and identifying various methodologies and power optimization techniques that have been implemented. With this information, a modified algorithm is proposed by substituting or eliminating certain elements from the layers of the algorithm. Through this, the proposed architecture not only achieves power optimization but also an area efficient model by eliminating unnecessary circuitry from the design. The proposed design was implemented using Xilinx ISE and synthesized using Synopsys Design Vision and Synopsys Primetime using the GSCL 45nm technology library.