A Novel Low Power Architecture for the Implementation of AES 128 Algorithm for Implantable Cardiac Devices

The increased usage of Internet of Things (IoT) devices exposes them to more external vulnerabilities. Over the years there have been many instances of data breaches occurring around the world. Pacemakers are no different and, in some cases, are more vulnerable to unwanted access. Pacemakers now come with wireless access allowing for easier communication feedback and programming for hospitals and doctors. In lab tests it has been shown a pacemaker can be hacked, however there are no reports of a real-world hack. There are many encryption methods being used for data security, one such method is Advanced Encryption Standard (AES). AES is one of the most popular and widely adopted symmetric encryption/decryption algorithms. As pacemaker technology advances, they are becoming smaller which leaves less room for batteries. The additional AES functionality consumes extra power in these already power constrained devices. This further reduces the lifespan of the batteries, thus making a low power implementation of AES critical. In iterative basic block AES architecture, encryption is performed using a 128-bit data path and is frequently designed for higher speed processing. This method is too costly and power inefficient for usage in implantable cardiac devices. This thesis introduces a novel Round Core Architecture designed to share processing blocks between the encryption and decryption processes, in order to reduce total hardware and total area leading to a reduction in overall power consumption. This goal is accomplished by decreasing the Round Core data path from 128-bits to 32-bits, with a focus on merging the core functions in the encryption and decryption data paths. Simulations of the proposed architecture, using 90nm and 45nm CMOS technology nodes, yielded area reductions of 92.39% and 90.96% respectively relative to the basic block architecture. Additionally, simulations yielded 78.34% and 74.14% average reduction respectively in overall power consumption of AES compared to the baseline design.