An Autonomous Per Thread Physical Register Allocation Technique for Simultaneous Multi-Threading Processors

Simultaneous Multi-Threading (SMT) is a technique used to improve the overall efficiency of superscalar computers by permitting multiple independent threads with shared key data path components to execute concurrently, thereby better utilizing the shared resources provided by the processor's architecture. With inter-thread sharing, which reduces the amount of registers needed in an SMT processor, a physical register file is made to be one of the most critically shared resources in the processor. Registers held by instructions of slow threads with overwhelming occupancy time of register file leads to resource monopoly, thereby slowing down, and sometimes blocking the progress of other faster threads, resulting in inefficient resource utilization and undesirable performance degradation. In this report, the new algorithm proposed dynamically allocates a portion of the rename registers to each thread (i.e. cap) in real time via an autonomous process that is dependent on the run-time behaviors of its average occupancy time of allocated registers (register hold time) and the rate of instructions committed (ICR), all within a preset observation window timeframe. To counter over-adjustment in the system, a global lower and upper limit range on cap values for individual thread is set. IPC improvements of up to 53%, 36% and 18% is achieved in a 4-threaded, 6-threaded and 8-threaded system respectively. Demonstrated also by harmonic IPC improvements of up to 30%, 30% and 29% for a 4-threaded, 6-threaded and 8-threaded system, execution fairness among threads is achieved with this technique.