Performance tradeoff of leakage reduction techniques in nanoscale CMOS circuits




Koppa Venkataswamy, Santosh Kumar

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In today's world, portable electronics thrives to achieve higher speed, lower power and lesser area. In the regime of improving performance and reducing the area, power was given least importance and had been ignored for quite some time. In current generation nanoscale CMOS technology, leakage power consumption has become a major concern and circuits are now designed considering leakage power as a major design factor. Nanoscale CMOS circuits incorporate high speed logic and high density memory circuits in a single chip making it hungry for power. To reduce the leakage power consumption in integrated circuits (ICs) several leakage reduction techniques have been proposed. Each technique has its own merits and demerits. This thesis examines the tradeoff of several leakage reduction techniques when applied to standard CMOS circuits such as adders, multipliers and memory.

Some of the important components of the current generation CMOS circuits are adders and memories. The 1-bit full adder is one of the most extensively used circuits and is a very important component in digital design applications such as ALU in microprocessors and micro controllers, DSP processors which is highly calculation intensive. One of the challenges in designing the current generation integrated circuits are the critical path of the ALUs which comprises of full adders, memory address generation circuits which uses full adders and the low latency memory itself. In the current generation of nanoscale ICs one of the challenges is to reduce the leakage power of the circuit. Low power, low area full adders are required for the portable devices and high speed full adders are required for computation intensive server processors, desktop processor and real time embedded systems. Hence a detailed analysis of all the full adder circuit topology is required to select the best full adder based on the applications and its trade off when leakage reduction techniques are used to build the circuit. This thesis investigates 32 different full adders starting from 10 transistor adder to the conventional 28 transistor full adder and effectively characterizes all the full adders based on its power and speed, with respect to different leakage reduction techniques for sub 100 nanometer technology nodes. This thesis also examines the effectiveness of several leakage reduction techniques for a case study of 8x8 Wallace multiplier. Several known leakage reduction techniques are applied to the Wallace multiplier and the performance tradeoff of the multiplier is analyzed.

To reduce the memory access latency, high density SRAMs are used as cache in current generation processors. Memories consume a large percentage of the area and power of the system. Memory circuits remain ON in retention mode (low power mode) for maximum amount of time to retain the data. All these factors make memory design one of the most important tasks in a system design. The speed and power consumed by the memories impact the system as a whole and hence reducing the power and increasing the speed of the memory circuit is of high importance. This thesis also examines the efficiency of using high-k metal gate MOSFETs for SRAM design applied with leakage reduction techniques.


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CMOS circuits, full adders, leakage, nanoscale, SRAM, wallace multiplier



Electrical and Computer Engineering