Management of shared resources in multi-threading / multi-core systems

dc.contributor.advisorLin, Wei-Ming
dc.contributor.authorZhang, Yilin
dc.contributor.committeeMemberJohn, Eugene
dc.contributor.committeeMemberLiu, Bao
dc.contributor.committeeMemberYe, Keying
dc.date.accessioned2024-03-08T17:41:06Z
dc.date.available2024-03-08T17:41:06Z
dc.date.issued2014
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractBased on the traditional superscalar processors, Simultaneous Multi-Threading (SMT) offers an improved mechanism to enhance the overall performance by exploiting Thread-Level Parallelism (TLP) to overcome the limits of Instruction-Level Parallelism (ILP), and a multi-core system with multiple independent processors is capable in utilizing job-level parallelism by allowing multiple jobs to be processed currently. The most common characteristic of parallel systems is the sharing of key datapath components among multiple independent threads/jobs in order to better utilize the resources. In an SMT system, due to the various characteristics of each thread, the occupation of the shared resources can be very unbalanced. Our research is aiming to solve this problem and to make efficient resource allocation among threads. Our investigation shows that among the resources in an SMT system, physical register file, Issue Queue (IQ) and write buffer are the most critical resources that are shared among threads. There are several approaches proposed in this dissertation: Register File Allocation, Instruction Recalling, Speculative Trace Control, Autonomous IQ Usage Control, Write Buffer Capping and Integrated Shared Resources Control. To better utilize the physical register file, we limit the maximal number of physical registers that a thread is allowed to occupy at any time, so as to eliminate the overwhelming occupation caused by a single thread. Several techniques have been proposed in order to improve the utilization of IQ: (1) to reduce the IQ occupation of the inactive thread, we introduce Instruction Recalling to remove those long-latency instructions; (2) to reduce the wastes of resources caused by the wrong-way trace due to a branch miss prediction, we propose an algorithm to control the amount of speculative instructions from a thread to be dispatched and executed in the pipeline, the so-called Speculative Trace Control technique; and (3) to remove the environment dependency of a technique, we introduced Autonomous Control to adjust the IQ distribution based on the real-time performance output. The write buffer is another shared resource which is easily unfairly occupied. Write Buffer Capping is a technique which prevents any threads from overwhelmingly occupying the write buffer by setting a cap value on the maximal amount of write buffer entries that a thread is allowed to take. The Integrated Shared Resource Management takes the above factors into consideration and manages the usage of the most critical shared resources (physical register file, IQ and write buffer) simultaneously for each thread, providing even significant enhancement with relative small hardware investment. In a multi-core system, memory and the interconnection network are shared among processors and their performances are key to the overall throughput of the system. In the last chapter we further extend our analysis on the impact that different interconnection networks impose on the whole system's overall performance. We show that the tradeoff between latency and concurrent access capacity may become a critical deciding factor in choosing the correct size of network for applications with different memory traffic demands.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent162 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9781321475227
dc.identifier.urihttps://hdl.handle.net/20.500.12588/6237
dc.languageen
dc.subjectIssue Queue
dc.subjectMulti-core
dc.subjectPhysical register file
dc.subjectSimultaneous Multi-threading
dc.subjectSpeculative execution
dc.subjectWrite buffer
dc.subject.classificationComputer engineering
dc.subject.lcshThreads (Computer programs)
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshMultiprocessors
dc.titleManagement of shared resources in multi-threading / multi-core systems
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy

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