Low power VLSI implementation of paired transform based FFT
The Fourier transformation is one of the most widely used tool in digital signal and image processing. In digital signal processing, this transform has led to the development of other fast discrete transforms such as Hartley transform, Hadamard transform, Discrete Fourier Transform etc. Discrete Fourier Transform is equivalent to continuous Fourier Transform defined over discrete time samples. Several efficient computer algorithms were proposed in the past for calculation of Discrete Fourier Transform (DFT) known as Fast Fourier Transform (FFT) algorithms. In Fourier Transform, the structure comprises of a unitary transformation also known Paired Transform. Paired Transform method is an advanced technique where the results are calculated in much earlier stages, making this technique more effective than the Fast Fourier Transform. Paired Transform can be further modified to reduce the computation time by Fast Paired Transform technique, by splitting the DFT differently. This research concentrates on the low power design, implementation and performance analysis comparison of Fast Fourier Transform algorithms. Radix-2, Paired Transform and Fast Paired Transform algorithms are the three algorithms considered in this thesis. HDL implementation of 4-, 8-, 16-, and 32-, 64- and 128-point algorithms for Radix-2 FFT, Paired and Fast Paired Transform with complex inputs is performed. Each N-point (N = 4, 8, 16, 32, 64, 128) design for three transforms is analyzed based on power, area and delay. In this research each design is realized by 180nm technology node. The results of simulation for Radix-2, Paired and Fast Paired algorithms are obtained from Cadence Soc Encounter RTL-to-GDSII. Simulation results shows that the Fast Paired Transform consumes less power, area and delay compared to other transforms investigated in this research. The optimization in the number of arithmetic operations in Fast Paired technique makes it more efficient for computation as well as hardware implementation.