Modified gate diffusion input technique based energy efficient Fused Multiplier-Adder

Date
2016
Authors
Reddy, G. Prashanth
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Abstract

Additions and multiplications are vital arithmetic operations and acts as building blocks for synthesizing all other operations. Adders and multipliers are extensively used circuit elements in Very Large Scale Integration (VLSI) systems such as Digital Signal Processors (DSP) and microprocessors. It is the core of many other operations like subtraction and division.

The objective of this thesis is to design an energy efficient 32-bit Fused Multiplier-Adder (FMA) in 32nm technology using Modified GDI (Gate Diffusion Input) technique. To this end, a Fused Multiplier-Adder (FMA) unit is designed and implemented based on the modified GDI technique, which overcomes the problem of the threshold drop in standard, GDI technique. The performance of the designed modified GDI based Fused Multiplier-Adder is analyzed and compared with the FMA realized using standard CMOS technology. A slight modification to AND, XOR and OR gate logic has been done to achieve full swing voltage [4] and these modified GDI gates were used in designing the Carry Look-Ahead adder and the Array Multiplier and the required connections were made to make the FMA. Predictive Technology Model (PTM) BSIM4 transistor models were used for all the simulations. The results of the simulations were analyzed and the trends in leakage power, dynamic power and delay were observed. The designed Fused Multiplier-Adder circuit using modified GDI technique, shows improvement in power, area and speed when compared to FMA using standard CMOS technology.

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Department
Electrical and Computer Engineering