Leakage Optimized Parallel Prefix Adders for Implantable Cardiac Devices

dc.contributor.advisorJohn, Eugene B.
dc.contributor.authorKhan, Adviya Saba
dc.contributor.committeeMemberKrishnan, Ram
dc.contributor.committeeMemberDuan, Lide
dc.date.accessioned2024-02-12T14:40:58Z
dc.date.available2024-02-12T14:40:58Z
dc.date.issued2018
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractDevelopment of implantable medical devices is always a unique challenge as it requires robust materials, versatile functionality, low battery power consumption, system delivery, and wireless communication all in one reliable yet low form factor. A pacemaker monitors the cardiac signals of the heart, calculates the need for artificial pacing, and generates electric impulses to synchronize the heart's rhythm. In a typical pacemaker, a dedicated microprocessor plays a prominent role in monitoring, pulse generation, and other required functionalities. The Arithmetic Logic Unit is one of the most important components in a microprocessor and relies heavily on adders with very low power consumption. The objective of this thesis is to find a suitable leakage optimized Parallel Prefix Adder among Brent-Kung Adder, Han-Carlson Adder, Knowles Adder, Kogge-Stone Adder, Ladner-Fischer Adder, and Sklansky Adder for implantable cardiac devices. The performance metrics considered for the analysis of adders are power, delay, and area. In this research, techniques such as High-Vt, Low-Vt and Standard-Vt versions of the SAED 90nm and slow-slow, typical-typical and fast-fast corners of NCSU 45nm process libraries are used for implementation of 16, 32, and 64-bit Parallel Prefix Adders. Multi-threshold Voltage Technique is also considered for power performance enhancement. TSMC 180nm technology is used for schematic and physical layout syntheses.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent99 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9780355957525
dc.identifier.urihttps://hdl.handle.net/20.500.12588/4068
dc.languageen
dc.subjectImplantable cardiac devices
dc.subjectLeakage power optimization
dc.subjectLow power
dc.subjectParallel Prefix Adders
dc.subject.classificationComputer engineering
dc.titleLeakage Optimized Parallel Prefix Adders for Implantable Cardiac Devices
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

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