Static noise margin and power dissipation analysis of various SRAM topologies

dc.contributor.advisorJohn, Eugene
dc.contributor.authorMishra, Prajna
dc.contributor.committeeMemberJohn, Eugene
dc.contributor.committeeMemberLin, Wei-Ming
dc.contributor.committeeMemberHansen, Lars
dc.date.accessioned2024-02-12T15:39:58Z
dc.date.available2024-02-12T15:39:58Z
dc.date.issued2013
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractThe increased demand for mobile devices has led to intense research efforts in the design and development of low power integrated circuits. Static Random Access Memory (SRAM) is a major component in modern high-performance digital systems such as microprocessors and Digital Signal Processors (DSPs) that are used in mobile devices. SRAM, the most widely used embedded memory, typically occupies the largest portion of the SoC die area and often dominates the total power consumption. Reducing power consumption of the embedded memory has been a major recent research focus. To that end several low power SRAM cells has been proposed. The objective of this paper is to analyze and compare various low power SRAM cells that are used for the design of low power embedded memory. In this research, 8 different 1 bit SRAM cells are compared in the basis of different performance metrics like dynamic power, leakage power, area, SNM, read delay and write delay. Those 8 different 1 bit SRAM cells that are used for this research are 4T loadless SRAM cell, 6T SRAM cell, 7T SRAM cell, 8T SRAM cell and 10T SRAM cell. There are 2 different designs each using 7T, 8T and 10T models and were labeled by Design 1 and Design 2 each respectively. Each 8 different cells are simulated using HSPICE for 45nm, 32nm and 22nm technology nodes. Predictive Technology Model (PTM) BSIM4 transistor models were used for all the simulations. Throughout the design and analysis VDD is kept at 1.2V. Based on the experimental results, the SRAM cell 7T Design 1 exhibited the best overall performance followed by the SRAM cell 8T Design1. Based on the previous 1 bit 8 different SRAMs experimental results, this research is also included with the comparison of simulation results of 1Kb 7T SRAM with conventional 1Kb 4T and 6T SRAM. The simulation of all 3 different 1Kb SRAMs are done by considering the different performance metrics like dynamic power, static power, area, Read 1 and Read 0 Delay, Write 1 and Write 0 Delay in 45nm, 32nm and 22nm PTM based technology node. Finally, this research is concluded with the comparison of simulation results for all 3 different 1Kb SRAMs in 3 different technology nodes. The overall results indicate that 7T Design1 SRAM exhibits better performance as compared to other SRAMs investigated in this research. The research results are expected to enable memory circuit designers to choose the appropriate SRAM cell for the required SNM and power consumption.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent120 pages
dc.format.mimetypeapplication/pdf
dc.identifier.urihttps://hdl.handle.net/20.500.12588/4534
dc.languageen
dc.subjectArea
dc.subjectDyanamic Power
dc.subjectRead Delay
dc.subjectStatic Noise Margin
dc.subjectStatic Power
dc.subjectWrite Delay
dc.subject.classificationComputer engineering
dc.titleStatic noise margin and power dissipation analysis of various SRAM topologies
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

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