Investigation of leakage reduction techniques for field programmable gate arrays




Nair, Pradeep Sreekantan

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Field Programmable Gate Arrays (FPGAs) are integrated circuits which can be reprogrammed. FPGAs are sold as pre-manufactured and tested products. A design that is implemented on an FPGA can be replaced by another design by reprogramming the FPGA with the help of reconfiguring hardware. Most of the modern FPGA architectures rely heavily on the use of Static Random Access Memory (SRAM) to achieve functionality and configuration and, therefore, are categorized as SRAM-based FPGAs.

The extra cost associated with the flexibility of an FPGA is that it makes a typical FPGA architecture prone to leakage. This is mainly due to the following reasons: Due to the flexibility available within the FPGA, large portions of the chip remain unutilized after a design has been implemented. Even within the parts that are utilized for design implementation, there are many interconnection and logic parts that remain underutilized most of the time. These factors contribute to the problem of leakage power dissipation in FPGAs. In order to address the challenge of leakage power dissipation in FPGAs, these issues have to be addressed. In this research work, techniques that help in curbing the problem of leakage power dissipation in FPGAs are investigated. The leakage power dissipation in the building blocks of a FPGA such as look-up tables, multiplexers and SRAM is analyzed and optimized.


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Digital Systems, FPGA, Leakage Reduction



Electrical and Computer Engineering