Issuing prioritization of instructions in the ready queue for superscalar processor




Gupta, Divya

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In SimpleScalar architecture, the default ready instruction scheduling policy gives out-of- order issuing priority to memory instructions, control instructions and long latency instructions by placing them on top of the Ready Queue upon their entry into the queue, whereas the regular instructions are sequentially positioned below them in increasing order of their program sequence. The use of this policy is justified in SimpleScalar documentation by – “this policy works well because branches pass through the machine quicker which works to reduce branch mis-prediction latencies, and very long latency instructions (such as loads and multiplies) get priority since they are very likely on the program's critical path”. However, if a memory instruction, control instruction or long latency instruction exists on top of the queue and is followed by the entry of a regular instruction, then irrespective of program sequence number or any other parameter, the regular instruction will be placed on top of the load/store instruction, which renders the later unimportant. This policy takes a toll on the CPU performance as other instructions that are dependent on these load/store or control or long latency instructions have to wait longer to be ready for execution. The purpose of this study was to implement the best possible scheduling policy, since it is crucial towards the overall performance of the system to ensure that instructions with higher dependencies are executed with top priority. Therefore, these producer instructions with level one dependency, should be placed on top of the Ready Queue or on top of others, which have few or no dependencies but occur earlier in the program sequence. In this research, we apply various scheduling techniques on different architectural system configurations; these configurations differ in terms of the number of resources provided. SimpleScalar simulator and SPEC CPU2006 benchmarks were used to simulate the scheduling policy and statistics of the Ready Queue instructions. Numerous algorithms were incorporated in the Ready Queue to alter the issuing priority and corresponding effects were noted for comparisons. It was found that, the system IPC was higher for architectures where memory, control and long-latency instructions were given issuing priority over regular instructions at all times, irrespective of the program sequence. Further improvements were observed upon sequential insertion of the memory, control and long-latency instructions, when long latency instructions were given a priority over the others.


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Computer Architecture, Issue Prioritization, Ready queue, Simplescalar simulator, Superscalar processor



Electrical and Computer Engineering