Prioritizing occupancy of write buffer in simultaneous multithreading processor

Date
2015
Authors
Lawal, Sherifdeen
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Abstract

Default algorithm at the commit stage of the SMT processor concentrates on equal opportunity for all threads to retire their instructions (round robin). However, it provides no control over how individual threads retired or committed store instructions to the write buffer. Throughput improvement in SMT can be achieved only when critical shared resources among temporally competing threads are efficiently controlled. Allowing any of the threads to overwhelm these resources not only leads to unfair thread processing but also may severely degrade overall system performance. Write buffer in SMT processor is one of the most critical shared resources and lack of balanced utilization of this buffer not only creates a bottleneck but also an irrefutable degradation to the entire system. Furthermore, due to its size constraint and potentially long occupancy latency from its data, it is a crucial component of the SMT processor in need of control and relief from pressure. In this paper, we show that, by giving a preferential entry into the write buffer in the commit stage, the overall system throughput is enhanced by an appreciable margin. An improvement in IPC of up to 30% and 130% is observed when the proposed technique is applied to a 4-threaded and 8-threaded SMT system, respectively.

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Keywords
Simultaneous Multi-threading, Superscalar, Write Buffer
Citation
Department
Electrical and Computer Engineering