Design and verification of a variable-latency SPARC V8 processor integer unit for cost and performance
Synchronous VLSI design requires all computations in a logic stage to complete in one clock cycle that determines the circuit speed. Technology scaling provides higher clock speed at the expense of introducing parametric variations at nanotechnology that results in performance variability due to timing soft errors. On the contrary, variable-latency design performs logic computations in a logic stage in a variable number of clock cycles where clock period is less than critical path delay. At the occurrences of timing violation variable-latency design allows multiple clock cycle to meet the timing requirement whereas it over-clocks for all other computations. This leads to an average latency and energy consumption improvement for a variable-latency VLSI circuit whereas timing improvement is not possible unless otherwise technology scaling is performed in a timing driven synchronous design. This thesis proposes, a generic minimum intrusion variable-latency design paradigm, signal probability based approximate prediction unit for cost and performance and an EDA flow with industry standard tools to implement variable-latency design. Proposed variable-latency design was implemented on open source SPARC V8 architecture compliant LEON2 processor integer unit in 45nm Nangate Open Cell Library. For a generic benchmark program, variable latency design achieves 28.05% timing improvement with 0.27% area improvement for a cost of 40.14% power overhead and energy consumption was increased by 0.83%. Simulating variable-latency processor for MiBench benchmark programs at optimum point of generic variable-latency design hardware shows 16%-24% timing and 0.1%-0.86% energy improvements at the expense of 19%-30% power overhead.