Resource control methods for multithreaded cores
| dc.contributor.advisor | Lin, Wei-Ming | |
| dc.contributor.author | Carroll, Shane | |
| dc.date.accessioned | 2024-02-09T19:29:19Z | |
| dc.date.available | 2024-02-09T19:29:19Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | In a simultaneous multithreaded system, a core's hardware may be shared among multiple threads in a single clock cycle. This simultaneous occupancy of hardware is implemented to exploit thread-level parallelism in addition to instruction-level parallelism. However, since any combination of threads which simultaneously occupy a series of hardware resources may proceed at different paces, this technique inevitably leads to resource starvation and a biased distribution of shared resources. This in turn leads to degraded overall system performance. Two notable shared resources are the issue queue and the write buffer. The issue queue acts as a collection of buffers for a core's functional units. Before an instruction may execute, it must first be dispatched to the issue queue, which in turn dispatches the instruction to an appropriate functional unit. A write buffer acts as an intermediary between a core's final pipeline stage and its data cache. The write buffer holds the values of committed store instructions while the appropriate cache lines are located and brought into memory. This thesis presents techniques to increase system performance in multithreaded cores by dynamically controlling how these resources are allocated to different threads. The proposed techniques were implemented in a simulation environment and were shown to have significant overall system performance improvement in the simulated environment. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 60 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9781321734577 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/2943 | |
| dc.language | en | |
| dc.subject | multithreaded | |
| dc.subject | multithreading | |
| dc.subject | simultaneous multithreaded | |
| dc.subject | simultaneous multithreading | |
| dc.subject | SMT | |
| dc.subject.classification | Computer engineering | |
| dc.subject.lcsh | Simultaneous multithreading processors | |
| dc.title | Resource control methods for multithreaded cores | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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