A survey of Electronic System Level based power estimation techniques for arbitary logic and processors

Power estimation of chips is imperative. To meet the low power requirements amid the configuration of new chip, power consumption has be regarded officially during the configuration of new chip. Electronic System Level (ESL) outline methodologies permit engineers to achieve design improvements on the latest designs more rapidly, efficient and economical than with customary RTL approach, by prototyping, debugging and analyzing complicated design systems before the RTL stage. This report presents a novel idea of surveying of the existing power estimation techniques at ESL level for arbitrary logic and processors.