Performance analysis of FinFET based nanoscale multiplier and divider circuits

Date

2014

Authors

Syam, Paromita

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Abstract

Conventional MOSFETs have inherent problems of large leakage currents and increasingly unreliable transistor characteristics. FinFET or MuGFETs (Multiple Gate Field Effect Transistors) have emerged as an effective alternative to the conventional bulk MOSFETs to continue scaling down to sub 32 nm regimes. Modern FinFETs are 3D structures that rise above the planar substrate. This allows the use of lower threshold voltages, which results in optimal switching speeds and power. The primary objective of this research is the design and performance analysis of several FinFET based multipliers and dividers. In this research, three multiplier algorithms and two divider algorithms have been analyzed and implemented. The performance of FinFET based circuits were compared to that of the planar CMOS based circuits. The multiplier algorithms that were analyzed include- Ripple Carry Array Multiplier, Linear Carry Save Array Multiplier and Wallace Tree Multiplier. The Divider algorithms implemented in the present work are- Restoring Divider and Non-Restoring Divider. All the multiplier algorithms were implemented for 8bit, 16bit and 32bit architectures each; whereas the divider algorithms were implemented for 8bit and 16bit architectures each. All the circuit combinations were simulated using HSPICE circuit simulator and were realized in 32nm, 20nm and 14nm technology nodes for simulations in FinFET and 32nm and 22nm technology nodes for simulations in MOSFET. For each of the multiplier and divider topologies that were simulated in both FinFET and MOSFET, the performance metrics that were measured, analyzed and compared are dynamic power, leakage power and delay penalties. It is observed, that in case of FinFET technology, the power consumption is much less compared to that of planar MOSFET based circuits. FinFET circuits also exhibited better delay performance compared to planar CMOS circuits. For both MOSFET and FinFET transistor models, Predictive Technology Model (PTM) BSIM4 (Berkeley Short-Channel IGFET MODEL) and Predictive Technology Model (PTM) BSIM-CMG (Berkeley Short-Channel IGFET MODEL Common Multi Gate) models have been used respectively for simulations.

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Keywords

FinFET, Linear Carry Save Array Multiplier, MOSFET, Non-Restoring Divider, Short Channel Effects, Wallace Tree Multiplier

Citation

Department

Electrical and Computer Engineering