Performance analysis of FinFET based nanoscale multiplier and divider circuits

dc.contributor.advisorJohn, Eugene
dc.contributor.authorSyam, Paromita
dc.contributor.committeeMemberLin, Wei-Ming
dc.contributor.committeeMemberHansen, Lars
dc.date.accessioned2024-03-08T15:44:04Z
dc.date.available2024-03-08T15:44:04Z
dc.date.issued2014
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractConventional MOSFETs have inherent problems of large leakage currents and increasingly unreliable transistor characteristics. FinFET or MuGFETs (Multiple Gate Field Effect Transistors) have emerged as an effective alternative to the conventional bulk MOSFETs to continue scaling down to sub 32 nm regimes. Modern FinFETs are 3D structures that rise above the planar substrate. This allows the use of lower threshold voltages, which results in optimal switching speeds and power. The primary objective of this research is the design and performance analysis of several FinFET based multipliers and dividers. In this research, three multiplier algorithms and two divider algorithms have been analyzed and implemented. The performance of FinFET based circuits were compared to that of the planar CMOS based circuits. The multiplier algorithms that were analyzed include- Ripple Carry Array Multiplier, Linear Carry Save Array Multiplier and Wallace Tree Multiplier. The Divider algorithms implemented in the present work are- Restoring Divider and Non-Restoring Divider. All the multiplier algorithms were implemented for 8bit, 16bit and 32bit architectures each; whereas the divider algorithms were implemented for 8bit and 16bit architectures each. All the circuit combinations were simulated using HSPICE circuit simulator and were realized in 32nm, 20nm and 14nm technology nodes for simulations in FinFET and 32nm and 22nm technology nodes for simulations in MOSFET. For each of the multiplier and divider topologies that were simulated in both FinFET and MOSFET, the performance metrics that were measured, analyzed and compared are dynamic power, leakage power and delay penalties. It is observed, that in case of FinFET technology, the power consumption is much less compared to that of planar MOSFET based circuits. FinFET circuits also exhibited better delay performance compared to planar CMOS circuits. For both MOSFET and FinFET transistor models, Predictive Technology Model (PTM) BSIM4 (Berkeley Short-Channel IGFET MODEL) and Predictive Technology Model (PTM) BSIM-CMG (Berkeley Short-Channel IGFET MODEL Common Multi Gate) models have been used respectively for simulations.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent102 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9781321194999
dc.identifier.urihttps://hdl.handle.net/20.500.12588/5670
dc.languageen
dc.subjectFinFET
dc.subjectLinear Carry Save Array Multiplier
dc.subjectMOSFET
dc.subjectNon-Restoring Divider
dc.subjectShort Channel Effects
dc.subjectWallace Tree Multiplier
dc.subject.classificationComputer engineering
dc.subject.classificationElectrical engineering
dc.titlePerformance analysis of FinFET based nanoscale multiplier and divider circuits
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

Files

Original bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
Syam_utsa_1283M_11422.pdf
Size:
1.88 MB
Format:
Adobe Portable Document Format