Early Branch Resolution through Hardware and Software
| dc.contributor.advisor | John, Eugene | |
| dc.contributor.author | Mariano, Paul | |
| dc.contributor.committeeMember | Lin, Wei-Ming | |
| dc.contributor.committeeMember | Duan, Lide | |
| dc.date.accessioned | 2024-02-12T15:40:00Z | |
| dc.date.available | 2019-05-15 | |
| dc.date.available | 2024-02-12T15:40:00Z | |
| dc.date.issued | 2017 | |
| dc.description | This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID. | |
| dc.description.abstract | Microprocessors are ubiquitous in almost every aspect of modern life. They are not only used in computers, but phones, cars and even things such as thermostats and refrigerators now use a processor of some sort. This is indicative of how important microprocessors and by extension microprocessor design is in the modern world. One of the main goals of modern microprocessor design is increasing the performance of the microprocessors. In other words, this means decreasing the time it takes a microprocessor to execute a program. Pipelining, a method commonly used to speed up the throughput of processors, cannot achieve optimal performance due to penalties from various dependencies. Control hazards are the result of dependencies due to branch instructions. Branch prediction techniques reduce the penalties associated with these control hazards. A tremendous amount of research has gone into branch prediction, and almost every modern microprocessor has some form of branch prediction. Still, there is currently no method that predicts branches with 100% certainty. Early branch resolution is the process of processing all of the relevant data before a branch instruction requires it. By doing this, it removes branch penalties altogether. This thesis proposes a new microarchitecture with the goal of achieving early branch resolution. To test the effectiveness of the proposed new microarchitecture, it is simulated in SimpleScalar. A new extended instruction set architecture (ISA) is introduced to direct the instructions to the new microarchitecture. In addition, the compiler is modified to translate the new instructions. The SPEC CPU2006 benchmarks are compiled both with and without theextended ISA and run on both the default and the extended microarchitecture. The results of the simulation suggest this goal is achieved with a drastic reduction in branch misprediction and a resultant decrease in program execution time. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 79 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9781369776416 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/4560 | |
| dc.language | en | |
| dc.subject | Early Branch Resolution | |
| dc.subject | Reducing Branch Penalties | |
| dc.subject.classification | Computer engineering | |
| dc.subject.classification | Electrical engineering | |
| dc.title | Early Branch Resolution through Hardware and Software | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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