Design, Implementation and Performance comparison of 32-bit nano scale ALU using various adder topologies

dc.contributor.advisorJohn, Eugene
dc.contributor.authorCheboli, Megha
dc.contributor.committeeMemberLin, Wei-Ming
dc.contributor.committeeMemberHansen, Lars
dc.date.accessioned2024-02-09T20:19:54Z
dc.date.available2024-02-09T20:19:54Z
dc.date.issued2013
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractThe constant need for enhancing the ability of the processor to handle complex processes has resulted in the integration of a number of processor cores on the chip. The load on the main processor is reduced by supplementing it with co-processors, which are designed to work on specific type of functions such as signal processing, graphics etc. One of the most basic components in any processor is the Arithmetic Logic Unit (ALU). The arithmetic and logic unit (ALU) is a digital circuit that performs integer, logical and decision operations; which are the final processing functions performed by a processor. The ALU architecture has a number of implications on the power consumption, delay and the area of the processor. The primary objective of this research is the design, implementation and performance analysis of a 32-bit ALU using various adder topologies. The three different adder topologies used in this research are, Carry Look Ahead Adder (CLA), Carry Select Adder (CSLA) and Kogge Stone Adder (KSA). The multiplier topologies used in this research are Ripple Carry Array Multiplier (RCAM) and the Carry Save Array Multiplier (CSAM) architectures. Different combinations of adder and multiplier topologies were used to design 9 different ALU topologies. The designed ALU topologies were analyzed based on power, delay and area. In this research the ALU and its sub-modules were realized using TSMC 65nm technology node. Using Cadence Encounter delay, area and power performance of various ALU topologies were obtained. Simulation studies show that for a power and area efficient application an ALU topology with a CLA as the adder and CSAM with RCA as a multiplier should be used. For an application where speed is the limiting factor, an ALU topology with KSA as an adder and CSAM with CLA as a multiplier is a better choice.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent114 pages
dc.format.mimetypeapplication/pdf
dc.identifier.urihttps://hdl.handle.net/20.500.12588/3187
dc.languageen
dc.subject.classificationComputer engineering
dc.titleDesign, Implementation and Performance comparison of 32-bit nano scale ALU using various adder topologies
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

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