A Performance-Based Adaptive Physical Register Capping System for Simultaneous Multi-Threading Processors
Simultaneous Multi-Threading (SMT) processors allows concurrent execution of multiple independent threads to increase the performance by having better resource utilization in comparison to superscalar processors. The Physical Register Rename File is a shared resource among all threads to map architectural registers to a physical register. Once all available physical register are use, then the system is stalled to add new instructions for execution until a thread de-allocates one or more physical registers. In this paper, we propose a capping system to partition the physical register to each thread such that threads that can execute more instructions during a time frame will be given more physical register to use. While preventing threads that execute more slowly will have lower occupancy in the register file. By doing this, an average improvement in IPC increases by 49.6%, 51.3% and 43% for 4/6/8-threads, respectively.