Accelerating scientific applications on reconfigurable computing systems

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dc.contributor.advisorLo, Chia-Tien Dan
dc.contributor.advisorPsarris, Kleanthis
dc.contributor.authorTai, Yi-Gang
dc.contributor.committeeMemberRobbins, Kay A.
dc.contributor.committeeMemberTosun, Ali Saman
dc.contributor.committeeMemberZhang, Weining
dc.date.accessioned2024-03-08T15:44:09Z
dc.date.available2024-03-08T15:44:09Z
dc.date.issued2011
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractAdvances in multi-core, many-core, and heterogeneous computing systems have created numerous possibilities of parallelization and hardware acceleration. With their exibility and abundant logic resources, reconfigurable computing systems, in particular systems based on field-programmable gate arrays (FPGAs), have become an attractive option as hardware accelerators. This dissertation studies acceleration of QR and LU matrix decompositions on FPGA-based reconfigurable computing systems, where there are few solutions for scalable floating-point matrix decompositions. First, exploring experiments are presented to reveal the characteristics regarding different embedded processor cores and system configurations on an FPGA-based system. Next, a vector reduction method termed delayed buffering is proposed. With its low latency and high operator pipeline utilization, the method accelerates matrix decomposition by improving composing vector reduction computation. Finally, with the delayed buffering reduction incorporated, using an enhanced tiled matrix decomposition algorithm to access off-chip memory and parallelizing the main decomposition loop for on-chip computation allow a single FPGA to perform better than two general-purpose processors plus a graphics processing unit (GPU) for matrix decomposition of size limited by the capacity of off-chip memory.
dc.description.departmentComputer Science
dc.format.extent100 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9781124877112
dc.identifier.urihttps://hdl.handle.net/20.500.12588/5682
dc.languageen
dc.subjectFPGA
dc.subjecthardware acceleration
dc.subjectLU decomposition
dc.subjectQR decomposition
dc.subjectreconfigurable computing system
dc.subjectvector reduction
dc.subject.classificationComputer science
dc.titleAccelerating scientific applications on reconfigurable computing systems
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentComputer Science
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy

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