Application of queuing theory on superscalar processors

The modern hardware design of a Superscalar processor includes Register Update Unit (RUU) which holds the instructions to be executed in the respective Functional Units and hence a queuing model can be applied to find the expected queue length for functional unit. This model of Superscalar consists of a component that models the relationship between the instructions issued per cycle, size of the instruction window under ideal conditions, Reservation station entries for each Functional unit depending on the different mix of instructions and issue rate. Simplescalar simulator and SPEC CPU2000 benchmarks are used to simulate the statistics of the RUU and a discrete Markov model is used to find the state transitions and queuing theory is applied to find the relationship between the length of RUU and number of functional units.