Modeling and characterization of ferroelectric materials in CMOS technology

The application of ferroelectric materials in semiconductor CMOS technology has been an area of interest due to the tunable permittivity of ferroelectric (FE) materials. Outside the commonly seen memory applications, considerable research attempts has been made towards integrating FE materials in sub-micron transistors. Reports of higher turn on current and increased gate capacitance are among the positive observations made in the past. The primary challenges in this integration approach appear in the form of shifted threshold and the negative effect of ferroelectric hysteresis on the I-V characteristics, restricting reliable circuit operation. In this research, a design methodology of Metal Insulator Ferroelectric Semiconductor Field Effect Transistor (MIFSFET) is presented. The novel structure of the MIFSFET includes a thin stack of ferroelectric and Hi-K materials at the gate, resulting in significant increase of driving current with nominal effect on the sub threshold region. Design considerations for different device parameters (FE thickness, EOT, Hi-k oxide) are explored.