Low energy computation methods for implantable cardiac pacemaker workloads

Date
2016
Authors
Noor, Safwat Mostafa
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Abstract

Embedded systems revolutionized our perception of computing and the way it integrates into our life. At present, one can find computing elements in a broad spectrum of applications, ranging from minuscule implantable devices to massive supercomputers. In the field of the im-plantable biomedical device, the integration of ultra-low power embedded processors vastly im-proved the quality and the capability of treatments. Within this group of devices, the implantable cardiac pacemaker stands out as a prime example of an efficient yet highly reliable embedded system. Steady progress in computer architecture and VLSI technology played a major role in improving the functionality, reliability, size, and battery life of modern cardiac pacemakers.

The next generation cardiac pacemakers are expected to evolve into smart connected de-vices, in sync with the ubiquitous trend of smart appliances. However, the path to future smart pacemakers has major challenges that must be addressed. The nature of the application inherently makes the cardiac pacemaker extremely resource constrained with mission critical functional specifications that must be met. The consumption of power and functional reliability are the pri-mary factors that governs the design of a pacemaker's system architecture. Although existing low-power design techniques are efficient and are regularly utilized in modern pacemakers to meet those goals, they fall short when it comes to solving the computational challenges anticipat-ed in a smart and connected pacemaker.

This research aims to develop low-energy computation methods and design methodologies that can enable future cardiac pacemakers to become a reality. By analyzing the existing and the anticipated new computational workloads of a smart cardiac pacemaker, innovative and scalable power-saving design techniques are presented. Appropriate ISA selection, application specific software and hardware level optimization methods and multipurpose functional units are devel-oped to reduce overall circuit switching and power consumption. By identifying overlapping computational steps and predictable data flow patterns present in most implantable cardiac pacemaker workloads, the proposed design methodologies promise enhanced performance and improvement in battery life. Applicability of the developed techniques is investigated and tested in the context of pacemaker signal processing, security, and reliability workloads. Practical gate level implementations of the proposed methods are created and accurate evaluation of the per-formance and power consumption is carried out.

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Keywords
AES, ASIC, Cardiac Pacemaker, Computation, FFT, Workload
Citation
Department
Electrical and Computer Engineering