Reliability and adaptive performance in VLSI circuits

dc.contributor.advisorLiu, Bao
dc.contributor.authorTeshome, Fiona
dc.contributor.committeeMemberJohn, Eugene
dc.contributor.committeeMemberHudson, Fred
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractThe transistor has come a long way since its inception in the mid-20 th century. None of the technological luxuries enjoyed today would have been possible had vacuum tubes persisted until now. Transistors have evolved and reached the nanometer range whereby they are packed into a small integrated circuit or commonly known as a chip by the millions, doubling in number about every two years as Moore's Law predicted. Howbeit, the urge to continually downsize transistors presented integrated circuit designers with challenges in various aspects among which are power dissipation, variability, and reliability. Although the latter two have not been the center of attention as the former, they are increasingly becoming pressing issues. Because of parametric variations, performance scalability has been on a standstill unable to simultaneously improve with the small technology nodes. Additionally, the small size of transistors has drastically elevated their exposure to cosmic ray strikes and alpha particles radiation which set the grounds for timing and logic errors that are catalysts for performance degradation. With the goal of achieving reliability and adaptive performance in the presence of timing and logic errors as well as parametric variations, based on the Strongly Fault Secure (SFS) properties, a study is done on new approaches: clock gating with an error detection signal and clock generation with outputs of a combinational logic block in delay-insensitive (DI) code together with a code word validity checker. Overall results indicate that DCVSL hybrid design has the best adaptive performance with 2.31X delay reduction, while area and power penalty are 2.05X and 2.88X, respectively.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent76 pages
dc.subject.classificationComputer engineering
dc.subject.classificationElectrical engineering
dc.titleReliability and adaptive performance in VLSI circuits
dcterms.accessRightspq_closed and Computer Engineering of Texas at San Antonio of Science


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