Minimum Intrusion Variable Latency VLSI Design for LEON 2 Processor
Traditional synchronous VLSI design requires that all computations in a logic stage complete in one clock cycle. This has created increasingly prevalent timing errors in recent technology nodes as technology scaling introduces increasingly significant parametric variations that result in an increasing performance variability. Alternatively, by allowing computations in a logic stage to complete in a variable number of clock cycles, variable-latency design provides relaxed timing constraints for average performance, area and energy consumption optimization. The existing variable-latency design techniques are either limited to arithmetic circuits or require dramatic design change. In this thesis, we propose a minimum-intrusion variable-latency VLSI design methodology based on completion prediction and clock gating. Our variable latency design methodology provides minimum intrusion to the existing design, precisely identifies the timing critical paths, and enables fine optimization for area, power, and performance tradeoffs. Our experiments demonstrate that the proposed variable-latency VLSI design methodology achieves up to 12.59% area reduction and 12.55% energy consumption reduction with the same latency for the LEON2 processor integer unit compared with traditional timing-driven design based on random inputs and the 45nm Nangate open cell library.