SNM analysis of 11NM shorted-gate and low-power 6T FinFET SRAM topologies

Date

2015

Authors

Vernor, Dusten

Journal Title

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Volume Title

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Abstract

Seven design metrics were studied and evaluated to determine each metric's effect on the noise immunity of a 6T FinFET SRAM memory cell, the effect on subthreshold leakage current, as well as the read and write delays and energy consumption. Comparisons to a shorted-gate design scheme reveal the trade-offs between choosing design metrics for low power consumption versus performance. Back-gate biasing schemes can be utilized to reduce subthreshold current by up to 99%. Back-gate biasing can also be tuned to minimize the effect on noise vulnerability. Back-gate biasing does significantly reduce the drive strength of the SRAM cell, which translates to higher read and write delays due to the weakened inversion layer of the transistors. Back-gate biasing the n-type (NFET) and p-type (PFET) transistors show a parabolic response in read and hold noise immunity. Transistor sizing can be used to increase the read and write margins of the memory cell, but with a cost of exponential subthreshold leakage current gain. Increasing the transistor sizing of the SRAM cell acts to maximize the read static noise margin, but negatively impacts the hold static noise margin. Of the two designs, increasing transistor sizing of the low-power SRAM cell shows a greater improvement in read SNM as well as a larger detriment to the hold SNM. Temperature is seen to have minimal impact on static noise margins, but an exponential impact on subthreshold leakage current. Supply voltage scaling is determined to have the biggest impact on both noise immunity and leakage current. Word-line voltage scaling is seen to greatly effect the read and write delays, but negatively impacts the read static noise margin for voltages above the supply voltage. With optimizing the read and hold static noise margin in mind, modifications to the design metrics are introduced and compared with the original designs in terms of performance and noise immunity in an attempt to maximize the read and hold static noise margin, while minimizing the negative impact these design parameters have in terms of power consumption and delay. A static noise margin optimized 6T FinFET SRAM cell is introduced for both shorted-gate and low-power designs, while mitigating the negative effects on performance, static leakage current, and read and write energy.

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Keywords

6T, FinFET, Low-Power, SRAM, Static Noise Margin, VLSI

Citation

Department

Electrical and Computer Engineering