New DFT designs for path delay fault identification

Date
2014
Authors
Dodda, Kokila
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Volume Title
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Abstract

Nanoscale VLSI design faces an unprecedented verification challenge. In particular, subtle parametric variations lead to uncertainties and performance variabilities for individual devices, which may be accumulated and lead to timing errors. Because such parametric variations cannot be captured accurately, simulation cannot give accurate performance estimate and post silicon validation is necessary for nanoscale high performance. The proposed methods in this thesis is the design of two new timing error-detecting sequential elements which are EDS with four clock signals and Modified Razor logic with double clock cycle time to the LEON2 Integer unit to detect timing errors from the simulation using C programs. The proposed EDS DFT technique detects all the timing error at a cost of 26.9% area increase for an open source SPARC v8 processor LEON2. The proposed modified Razor logic detects all the timing error at a cost of 29.12% area increase for an open source SPARC v8 processor LEON2. The detected timing errors are less for proposed DFT modified Razor logic techniques is 165 because of double clock cycle where as DFT EDS sequential element is 166 timing errors. The other proposed methods are DFT LSSD technique and modified Razor logic with scan chain to detect the path delay faults for open source SPARC v8 LEON2 integer unit with BIST test pattern generator. The proposed DFT LSSD sequential elements detects the all timing error at a cost of 30.14% area increase for LEON2 Integer unit and detected timing errors for DFT LSSD technique is 248. The proposed modified Razor logic with Scan chain for LEON2 integer unit with BIST test pattern generation detects all the timing error at an cost of 28.93% area increase and detected timing errors from simulation is 241. Based on detected timing errors the proposed DFT modified Razor logic with and EDS sequential element provides a less detected timing errors compared to LSSD technique and modified Razor logic with scan chain detects all timing errors at an increase of 31% detection for open source SPARC v8 LEON2 with BIST.

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Keywords
BIST, EDS, LSSD, MODIFIED RAZOR LOGIC, TIMING ERRORS
Citation
Department
Electrical and Computer Engineering