A Statistical Ftechin Approach for Effective Management of Physical Register File in Simulatenous Multi Threading Processors
Simultaneous Multi-Threading (SMT) is a processor design technique that supports concurrent execution of instructions from multiple threads in every cycle by sharing the key datapath components. Efficient utilization of the shared resources is critical to achieving high-performance gain. In the SMT architecture, the physical register file is partially shared, and this inter-thread sharing of the physical registers reduces the number of registers required in the SMT processors than needed in deploying multiple superscalar processors to achieve a similar throughput. However, overwhelming occupancy of the physical register file by the slower threads can lead to the shortage of registers available for the other threads in the system and thus degrade the overall performance of the system. In this paper, we propose an intelligent fetching algorithm for the effective management of the partially shared physical register file. We demonstrate that by suspending the threads with the higher register hold time in the fetch stage can improve the overall system performance by a considerable margin. An improvement of up to 77% and 63% is achieved when the proposed scheme is applied to the 4-threaded and the 8-threaded system respectively. This fetching technique does not cause starvation of threads and achieve a high degree of execution fairness as demonstrated by the Harmonic IPC improvement of up to 90% and 57% for the 4-threaded and 8-threaded systems. Besides, the throughput of a 4-threaded system with 160 register file entries is comparable to the performance of default system with 256 register entries indicating a resource saving of 60%.
Keywords: Simultaneous Multi-Threading, Superscalar, Physical Register File, Fetch Stage