A Statistical Fetching Approach for Effective Management of Physical Register File in Simulatenous Multi Threading Processors

dc.contributor.advisorLin, Wei-Ming
dc.contributor.authorRamanathan, Madhava Krishnan
dc.contributor.committeeMemberLee, Wonjun
dc.contributor.committeeMemberDuan, Lide
dc.date.accessioned2024-02-12T19:52:25Z
dc.date.available2017-11-15
dc.date.available2024-02-12T19:52:25Z
dc.date.issued2017
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractSimultaneous Multi-Threading (SMT) is a processor design technique that supports concurrent execution of instructions from multiple threads in every cycle by sharing the key datapath components. Efficient utilization of the shared resources is critical to achieving high-performance gain. In the SMT architecture, the physical register file is partially shared, and this inter-thread sharing of the physical registers reduces the number of registers required in the SMT processors than needed in deploying multiple superscalar processors to achieve a similar throughput. However, overwhelming occupancy of the physical register file by the slower threads can lead to the shortage of registers available for the other threads in the system and thus degrade the overall performance of the system. In this paper, we propose an intelligent fetching algorithm for the effective management of the partially shared physical register file. We demonstrate that by suspending the threads with the higher register hold time in the fetch stage can improve the overall system performance by a considerable margin. An improvement of up to 77% and 63% is achieved when the proposed scheme is applied to the 4-threaded and the 8-threaded system respectively. This fetching technique does not cause starvation of threads and achieve a high degree of execution fairness as demonstrated by the Harmonic IPC improvement of up to 90% and 57% for the 4-threaded and 8-threaded systems. Besides, the throughput of a 4-threaded system with 160 register file entries is comparable to the performance of default system with 256 register entries indicating a resource saving of 60%.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent51 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9781369775655
dc.identifier.urihttps://hdl.handle.net/20.500.12588/5213
dc.languageen
dc.subjectSimultaneous Multi-Threading
dc.subjectSuperscalar
dc.subjectPhysical Register File
dc.subjectFetch Stage
dc.subject.classificationComputer engineering
dc.titleA Statistical Fetching Approach for Effective Management of Physical Register File in Simulatenous Multi Threading Processors
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

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