Design and realization of low power CMOS dividers

dc.contributor.advisorJohn, Eugene
dc.contributor.authorYen, Kai Hsien
dc.contributor.committeeMemberLin, Wei-Ming
dc.contributor.committeeMemberLee, Byeong Kil
dc.date.accessioned2024-03-08T17:34:33Z
dc.date.available2024-03-08T17:34:33Z
dc.date.issued2012
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractAll modern processors, including general purpose microprocessors, digital signal processors and GPUs contain an Arithmetic Logic Unit (ALU). The computing efficiency of modern processors mainly depends of the efficiency of the ALU. Modern ALUs can perform several complex functions including multiplication and division. Compared to addition, subtraction or multiplication, division is a less frequently used operation. Special purpose processors, such as DSPs use division operation to increase the speed performance. In the past, the primary focus in the design of the dividers was on circuit speed. However, low power requirement has become more and more important in recent years. The primary objective of this research is the design and realization of low power CMOS dividers using efficient adder modules. In this research 3 divider algorithms viz. Restoring Divider, Non-Restoring Divider and the SRT (Sweeney, Robertson, and Tocher) divider were analyzed. Adders are one of the key building blocks in the realization of a divider algorithm. In this research several adder modules were analyzed to identify the optimal adder modules that can be used for the realization of the divider algorithms. The performance metrics considered for the analysis of the adders are: power, delay and area. This research also proposes design modifications for one of the existing adder circuits to achieve better forms. In this research the CMOS dividers were realized using TSMC 65 and 40 nm technologies. For performance comparison, the dividers were realized using various adder modules. Using simulation studies, delay, area and power performance of the various adder modules and the dividers realized using these adder modules were obtained. It was observed that the divider algorithms realized using Low Power Carry Select Adder (LPCSA) and the Speculative Approximation Carry Look-ahead Adder (SACLA) have better circuit characteristics compared to dividers realized using other adder modules.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent88 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9781267616234
dc.identifier.urihttps://hdl.handle.net/20.500.12588/6062
dc.languageen
dc.subject.classificationElectrical engineering
dc.titleDesign and realization of low power CMOS dividers
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

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