Resource Optimization in Multithreaded and Multicore Architectures

This dissertation presents research pertaining to resource optimization in multithreaded and multicore CPU architectures. Chapter 1 introduces the area of research and provides the basic background of the work herein. Chapter 2 models a CPU's issue queue and functional unit configuration as a novel queuing network. Solving for this network reveals insightful and useful information about the efficiency of a system's configuration, and provides a novel contribution to queuing theory as well. Chapter 3 presents research which exploits invalidated cache space in CMP systems. It is shown that in CMP systems, a large amount of cache space is typically invalidated. A novel technique is proposed to exploit that invalidated cache space to decrease miss rate and improve CMP system performance. Chapter 4 presents research that optimizes round-robin scheduling in SMT systems. In this chapter it is shown that round robin can lead to resource starvation in SMT, but this can be solved by adjusting the ordering of round robin at runtime. Chapter 5 presents research that uses embedded machine learning techniques to intelligently pause inefficient threads in an SMT pipeline to improve overall performance. Chapter 6 presents a novel algorithm to augment cache replacement policies to decrease cache miss rates. It is shown that prioritizing the insertion of cache lines into an LRU queue can improve system performance over baseline LRU with little overhead. Together, these chapters provide novel contributions to CPU resource optimization.