The implementation of integer-slant transform in FPGA device
Orthogonal transforms have revolutionized the signal processing industry especially in the field of electronic imagery. The wide growth of production has increased demand for more desirable qualities and capabilities that exist as properties in few orthogonal transforms such as Discrete Cosine Transform DCT which is widely used for image and video compression applications and is adopted by many international standards such as JPEG, MPEG1, MPEG2,etc. However it is difficult to satisfy the requirement for real-time by software owing to its heavy quantity of computing. Therefore, a hardware method is adopted to satisfy the requirement for speed in many practical applications.. In fact, in known perception, hardware serves as a platform for software and this is the main reason for its existence. However, with the recent developments in electronics technology during the last decades this perception has changed letting the hardware systems serve a full solution to most of the electronic systems.
This thesis describes the FPGA implementation of two dimensional Integer-Slant Transform processor with Verilog HDL for application of image processing. The row-column decomposition algorithm and pipelining are used to produce the high quality circuit design with optimized clock frequency when implemented in Xilinx Virtex-4 .The thesis is encouraging the adoption of the Integer-Slant Transform as an alternative to the widely used DCT in image processing for specific applications, because of its similar energy compaction property and the fact that the slant basis vector is tailored to achieve optimal representation for images with gradual brightness variation along the image line.