Hardware accelerators for software GPS receivers

Date
2012
Authors
Kinjarapu, Dushyanth
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Abstract

With the development of powerful computational resources such as Digital Signal Processors and Field Programmable Gate Arrays, it has become possible to utilize many radio functions via software and hardware. This is the underneath concept of an up-coming technology of Software Defined Radio. In this Thesis, how Software Defined Radio platform provides a great deal of flexibility to modify the approaches and test new algorithms for higher reliability and better accuracy for software GPS (Global Positioning System) receiver development at a less cost. USRP (Universal serial Radio peripheral) and NI RF analyzer are the front end hardware kits used to capture the radio frequency signal and stream the converted Baseband signal from hardware to host. GNU Radio and LabVIEW software are to be installed on the host/PC side to apply digital signal processing techniques on the Baseband signal to extract the information in real time basis.

GPS-SDR is the open source software GPS core framework developed on GNU Radio software API for GPS receiver applications. Combining this software with USRP1 RF front end board a real time software GPS receiver system is setup for our research. This real time GPS receiver system is our reference for further Hardware implementations of GPS Algorithms. The acquisition search and correlations in tracking are the bottle necks of GPS receiver performance. We tested the performance efficiency of complete software GPS receiver with advanced FFT based block acquisition and advanced Block correlator algorithms on this real time test bed.

In recent days RF front end hardware vendors are providing different featured RF boards with different hardware solutions capabilities for custom applications. For example NI Flex RIO, USRP-N210 front end hardware boards are open to implement custom FPGA hardware applications. In LabVIEW Host-Target based FPGA environment, complex signal processing tasks of FPGA hardware can be delegated to FPGA placed on the front end hardware from the host environment. So, FFT based Block Acquisition and Advanced Block correlator of tracking in software are implemented in Verilog HDL and with some optimizations in the design of Block correlator we even designed Parallel Block correlator for GPS receiver tracking. In order to integrate our GPS accelerators developed on Xilinx ISE simulator into LabVIEW FPGA Environment, we used IP node (CLIP node) modules as an interface node to integrate our custom developed accelerators into LabVIEW FPGA. So, the hardware blocks like acquisition and Block correlator are integrated into LabVIEW FPGA modules and can be used like other LabVIEW FPGA modules in GPS receiver application development. Experimental results and performance comparison results give more insight of the Hardware accelerators requirement for SDR platforms.

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This item is available only to currently enrolled UTSA students, faculty or staff.
Keywords
Correlators, GPS, NI FPGA
Citation
Department
Electrical and Computer Engineering