Integer Register Renaming with Suspension Technique for SMT




Zhang, Zhexin

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Comparing to the basic processor architecture, instructions from more than one thread can be executed in any given pipeline stage concurrently in the Simultaneous Multi-threading Processor (SMT). SMT must have a larger register file than basic processors so that it can hold data from multiple threads. However, the shared resources have a limitation. Hence, focusing on the public shared resources, which apparently plays a very important role in the overall performance, is the key point to improve the overall performance.

In this thesis, register file is selected as the foothold because in the renaming stage, the lim- ited number of physical registers is obviously a bottleneck. The proposed method in this thesis is applying an architectural-level integer physical register file allocation algorithm to utilize the resources more efficiently. Here we set windows with a fixed size. At the end of each window, the register file utilization for each thread and the overall utilization are calculated. And once the overall utilization exceeds the preset threshold, suspension is executed in the next window. Again and again, until the overall utilization becomes lower than the threshold. If the overall utilization is lower than the threshold, all the suspended threads will be added back. With this simple algorithm, we can realize a great improvement of throughput. The simulator here we used is a modified M- sim, and our simulations tell us that we can gain up to 14.6% improvements on IPC (instructions per clock cycle) without sacrificing total fairness for all the threads we executed.


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register renaming, SMT



Electrical and Computer Engineering