A Low Power FPGA Implementation of the 128-bit AES Algorithm

Date

2018

Authors

Thakkar, Himanshu Jayantilal

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Abstract

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) which was considered to be insecure because of its vulnerability to brute force attack. DES's 56-bit key was no longer big enough to prevent brute force attack.

Presently AES is the most widely used cryptographic algorithm. The Advanced Encryption Standard (AES) is a symmetric-key encryption standard. Over the years, many research and modification has been made to make AES stronger and better in terms of security, speed of implementation and usefulness. However, with the growing use of the internet and handheld devices, power efficient AES algorithm has become a major design issue. The objective of this thesis is to develop low power AES implementation techniques. By analyzing the internal structures of the AES algorithm this research proposes a new low power AES algorithm implementation. The proposed low power algorithm presents a new method to implement function of rounds in a way that uses reduced number of steps to finish the implementation. The modified proposed algorithm uses less state registers that are needed to store the intermediate results of rounds which saves lots of circuitry which ultimately leads to reduction in power. The proposed algorithm is implemented in Altera FPGA to verify the functionality and implemented in 45 and 90 nm technology nodes to analyze and compare the power performance with respect to the original AES algorithm.

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Keywords

128-BIT, AES ALGORITHM, FPGA, IMPLEMENTATION, LOW POWER

Citation

Department

Electrical and Computer Engineering