Leakage power minimization of nanoscale CMOS multipliers

Date
2010
Authors
Atikunnabi, A. M.
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Abstract

Recently CMOS (complementary metal oxide semiconductor) circuits have been aggressively and efficiently designed for the better performance and less power usage especially for small sized handheld devices. A vast research has been initiated and the outcome of these researches is making the technology better day by day. The popular demand of drastically downsized high performance devices has been made possible by modulating multiple device parameters including the power supply, threshold voltage, transistor channel length etc. One of the main challenges in this design effort is to save as much power as possible to improve the battery life. The recent research has introduced some very efficient techniques to reduce the leakage power of the small sized devices. These techniques also have some antagonistic effects. Depending on the technique applied and the status of all other parameters of the device, it may experience little performance degradation, longer delay time or more power consumption as leakage power or dynamic power. Therefore properly understanding the technology scaling, effect of different modules in a system, high-end techniques to reduce power consumption and their proper use and the efficient tradeoff between power and performance of the device may allow the intelligent selection of such electronic circuits and devices for designing the system with desired performance rating.

In this research, different leakage reducing techniques were applied to different multipliers topologies of varying bit length (4 bit and 8 bit). The multipliers topologies that were investigated are: ripple carry array multiplier, carry save multiplier, Baugh Wooley multiplier and the Wallace tree multiplier. Full adders are main functional units in multipliers. To investigate the performance of these multipliers in terms of leakage power, dynamic power and delay using different full adders, all the multipliers were realized using conventional 28 transistor full adder, Static Energy Recovery 10 transistor (SERF) adder, 16 transistor full adder and 18 transistor full adder and the performance analyzed. The leakage power of the multipliers were characterized for technology scaling and simulated for 45nm, 32nm and 22nm technology nodes. Leakage reduction techniques such as multi-threshold voltage, long channel devices and power gating technique were applied to reduce the leakage power consumption of the multipliers. All the simulations in this research were done using HSPICE circuit simulator. For MOSFET transistor models, Predictive Technology Model (PTM) BSIM (Berkeley Short-channel IGFET Model) model files were used.

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This item is available only to currently enrolled UTSA students, faculty or staff.
Keywords
Digital Multipliers, Leakage power, Leakage reduction, Long channel, MTCMOS, Power gating
Citation
Department
Electrical and Computer Engineering