Victim Cache and Quota Victim Cache Performance Impact on Simultaneous Multithreaded Systems

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dc.contributor.advisorLin, Wei-Ming
dc.contributor.authorMielke, Robert
dc.contributor.committeeMemberJohn, Eugene
dc.contributor.committeeMemberKrishnan, Ram
dc.date.accessioned2024-01-26T23:08:58Z
dc.date.available2024-01-26T23:08:58Z
dc.date.issued2022
dc.descriptionThe author has granted permission for their work to be available to the general public.
dc.description.abstractSimultaneous multithreading, or SMT, uses a superscalar CPU running multiple threads to efficiently use a CPU. A key aspect of SMT is the sharing of resources, such as cache, between the threads to provide an efficiency gain over adding additional cores with private resources. Shared cache optimization allows for higher CPU performance by reducing the time wasted from cache misses. A victim cache and a modified victim cache utilizing a quota system were tested to see the instruction per cycle performance impact on a SMT system. The victim cache was added between the L1 and L2 caches and was tested in a single, double, and quadruple threaded case with mixes from the SPEC2006 benchmarks. The quota system victim cache was created specifically for SMT systems and was created to prevent greedier threads from using all of the victim cache, depriving the other threads of its benefits. The victim cache always generated higher IPC performance, but the magnitude decreased as the L1 cache grew, and increased with additional threads. With the quota modification, more performance than that of the victim cache was added, but the magnitude decreased with additional threads. Overall, the victim cache could be used to economically add performance to a system with a small L1 cache. The quota system did not generate enough additional performance to justify its additional expense, and could potentially be replaced with a partitioned victim cache.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent44 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9798358492417
dc.identifier.urihttps://hdl.handle.net/20.500.12588/2720
dc.languageen
dc.subjectSimultaneous Multithreading
dc.subjectSMT
dc.subjectSuperscalar
dc.subjectVictim Cache
dc.subject.classificationElectrical engineering
dc.titleVictim Cache and Quota Victim Cache Performance Impact on Simultaneous Multithreaded Systems
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_OA
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

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