A high level synthesis of GPS acquisition
With increasing complexity of system on chip designs, it is becoming harder to generate register transfer level structure. High level synthesis tools have become the tool of choice for designing ASSIC/FPGA's. A High level synthesis tool converts the algorithmic specification of a digital system to register transfer level (RTL). This thesis talks in detail on how a High level synthesis tool simplifies the design of large & complex hardware thereby improving the speed of a GPS Acquisition. Main goal of this research is to improve the performance of a GPS Acquisition by converting the algorithm code of the respective design to RTL design Algorithm.