A fast asynchronous approximate adder with error correction
Integer addition is the most important process used in computer systems and related applications, since it is the fundamental process used in all other integer and floating point arithmetic operations. Addition process is also used in the Microprocessor to calculate the address of the operands, instructions, memory storage etc. Many adder designs have been proposed in order to enhance the overall system performance. Approximation has proven to be a very effective approach which results in faster outputs compared to non-approximation techniques, even though it has the intrinsic drawback of producing a potentially incorrect result. This thesis proposes an approximate adder design with an error correction capability incorporated. Due to its built-in completion-detection mechanism, the proposed design is suitable for an asynchronous or variable-latency processing environment, and can deliver an expected completion time much shorter than all well-known parallel adders. Three different adder topologies viz. the Brent-Kung adder, Kogge-Stone adder and Approximate Adder with Error Correction were designed for 32-bit addition and each circuit was simulated using HSPICE for the 45nm, 65nm, 90nm and 180nm technology nodes. Predictive Technology Model (PTM) BSIM4 transistor models were used for all the simulations. The results of the simulations were analyzed and the trends in leakage power, dynamic power and delay among adders implemented were observed. The overall results indicate that the use of Approximate Adder with Error Correction resulted in less power consumption and fewer delay among well-known parallel adders, i.e., Brent-Kung and Kogge-Stone adders.