Analysis of shared memory in multi-core systems

dc.contributor.advisorLin, Wei-Ming
dc.contributor.authorV. S. L. V. N, Jaya Chaitanya
dc.contributor.committeeMemberLiu, Bao
dc.contributor.committeeMemberDuan, Lide
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractIn a multi-core system, the memory hierarchy and the interconnection network play a dominant role in deciding the performance of the system. In this research, we analyze the dependence of system performance on the interconnection network and memory hierarchy using a set of scientific and engineering workloads. A configuration with a smaller network has low memory access latency, but is more susceptible to memory access conflicts due to fewer memory banks. The extra delay originated from the concurrent memory access conflicts may offset the benefit of shorter latency. So, in this case a larger network with more number of memory banks can benefit from high number of concurrent memory access. This analysis reveals an important tradeoff between employing different sizes of network. Cache sharing on a multi-core processor is usually competitive. Cache coherence problems associated with private caches and the improvement in performance with sharing is analyzed in the last chapter.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent44 pages
dc.subjectApllied sciences
dc.subject.classificationComputer engineering
dc.subject.lcshEmbedded computer systems
dc.subject.lcshCache memory
dc.titleAnalysis of shared memory in multi-core systems
dcterms.accessRightspq_closed and Computer Engineering of Texas at San Antonio of Science


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