Two-phase latch-based BTWC VLSI design
| dc.contributor.advisor | Liu, Bao | |
| dc.contributor.author | Wang, Xutao | |
| dc.contributor.committeeMember | Lin, Wei-Ming | |
| dc.contributor.committeeMember | Duan, Lide | |
| dc.date.accessioned | 2024-03-08T17:35:30Z | |
| dc.date.available | 2024-03-08T17:35:30Z | |
| dc.date.issued | 2015 | |
| dc.description | This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID. | |
| dc.description.abstract | We combine retiming algorithm and better than worst case design to improve performance for a circuit. The performance benefits of latch-based design have been known for more and more synchronous VLSI designers. Specially, Latch-based design can be used in high-speed circuits due to time borrowing. However, compare with FF-based design, the performance result of the existing latch-based design are significantly improved based on limited clock cycle number. If there exists multi-cycle path and the number of clock cycle tends to endless, the methodology of fixed-phase retiming cannot improve performance significantly. Thus, it leads that latch-based design only can be applied in a few applications. In order to remove these limitations for making latch-based design more widely in applications and obtain acceptable cost, we present improved design techniques and novel algorithm to solve issues raised above. They include (1) a fixed-phase retiming algorithm for optimal latch insertion point identification which consider cost for current circuit, (2) a novel prediction unit structure which can be used for loop path which considers the endless clock cycle numbers. Our experimental results based on ISCAS'87 sequential benchmark show that our proposed two-phase latch-based telescopic design achieves an average of 31.55% performance improvement at cost of 6.2% area increase compared with traditional flip-flop-based design produced by Synopsys Design Compiler depends on the circuit structure. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 82 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9781321736991 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/6120 | |
| dc.language | en | |
| dc.subject | Applied sciences | |
| dc.subject.classification | Electrical engineering | |
| dc.subject.lcsh | Integrated circuits -- Very large scale integration -- Design and construction | |
| dc.title | Two-phase latch-based BTWC VLSI design | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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