Hardware Implementation and Performance Evaluation of K-Means and K-Means++ Clustering Algorithms

Date

2019

Authors

Singh, Manisha

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Abstract

The tremendous increase in complex unbounded dynamic data in the fields of geology, health, image processing, climatology, network security, etc. requires high speed and performance in data processing for analyzing big data. Current big data analysis algorithms are software implementation based and are not sufficient for processing and analyzing the data efficiently. Big data analysis algorithm involves data mining which partitions and clusters similar data into meaningful groups. The objective of this study is to provide big data analysis hardware implementation of the K-means and K-means++ clustering algorithms which are used to cluster similar data into groups and compare the cluster forming approach of both algorithms. Both algorithms use a state machine to process 3-dimensional data vectors and place them into a meaningful cluster after a fixed number of iterations and indicate final processed cluster data vectors by generating an interrupt. These algorithms are implemented in the Verilog hardware description language. Synthesis of both the ASIC design is done with Xilinx ISE Design Suite 13.4 using 45nm and 90nm technology nodes to calculate the gate count, power, delay, and area. Finally, the result of this research shows that the hardware implementation of K-means ++ puts the data vectors more meaningfully than K-means but at the cost of extra hardware.

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Department

Electrical and Computer Engineering