Optimizing Write Buffer Resource Sharing and Reducing Cache-miss Induced Instructions in Simultaneous Multi-threading Processors

Simultaneous Multi-Threading (SMT) is a processor design technique that offers improved resource utilization and higher instruction throughput by concurrently executing multiple threads and sharing key data path components. Its performance benefit comes from its capacity to dynamically allocate resources to the thread requiring them in each cycle. However, efficient distribution of critical shared resources, such as the write buffer, is essential for optimal performance. Threads characterized by a high incidence of long-latency cache misses dominating the write buffer’s resources can impact system performance. In some instances, the entire write buffer is occupied by store instructions that are all cache miss long latency instructions. Under such circumstances, it’s possible that a specific thread could monopolize the majority of the write buffer resources, leading to stalls for other threads. This thesis project proposes a method that addresses this issue by reducing the number of cache miss store instructions residing in the write buffer. The proposed allocation technique is considered a modification to the commit stage of the default algorithm by imposing a very simple control mechanism on assigning the write buffer entries. Specifically, this is achieved by reserving some write buffer entries for threads that have cache hit store instructions ready to be committed. The proposed method improved system performance on average by 10.5% to 47%, contingent on workload size and system configuration, ensuring fair execution among threads. In summary, the proposed algorithm provides a promising approach to mitigating performance issues related to write buffer utilization in SMT processors.