Sensitivity analysis on impact of hardware resources in SMT processors
The microprocessor performance is increased by allowing multiple threads per clock cycle to issue instructions in Simultaneous multithreading processors. Branch prediction and shared hardware resources are the key components of processor performance. Some of the techniques affect the performance in SMT Processors even if the shared hardware resources are high. Evaluating the effect of parameters like cache, physical register sizes, Issue Queue, Instruction fetch policies and branch prediction accuracy on the performance improvement in the SMT processors demonstrates the efficacy of hardware resources among the threads.
This research is oriented towards the analysis on the current fetch policies and hardware resources in SMT processors. The optimization of overall throughput and or fairness depends on how the running threads are executed and the resource utilization among the running threads. The performance of a processor is based on the fetch policy used and the workloads executed among the threads.