VLSI design for reliability and security in nanoscale technology
| dc.contributor.advisor | Lin, Wei-Ming | |
| dc.contributor.author | Maleki, Milad | |
| dc.contributor.committeeMember | White, Gregory B. | |
| dc.contributor.committeeMember | Duan, Lide | |
| dc.contributor.committeeMember | Lee, Wonjun | |
| dc.date.accessioned | 2024-02-12T14:52:44Z | |
| dc.date.available | 2016-11-06 | |
| dc.date.available | 2024-02-12T14:52:44Z | |
| dc.date.issued | 2016 | |
| dc.description | This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID. | |
| dc.description.abstract | As VLSI technology scales into the nanometer domain, and with the emergence of Internet-of-Things/Cyber-Physical Systems, VLSI systems are subject to growing variability and reliability challenges and security threats. Specifically, increasingly significant parametric variations from the manufacturing process, runtime system and surrounding environment lead to prevalent component performance variations, logic stage timing violations and system malfunction. IoT/CPS components are further subject to network attacks, physical attacks and supply chain attacks. Automotive electronics is one exemplary domain, which entails high level of both reliability and security. My dissertation work includes development of several timing error-resilient/adaptive performance VLSI design and security threat mitigation techniques. Specifically, in the first part of my dissertation, I propose a minimum-intrusion variable-latency VLSI design methodology based on completion prediction and clock gating. Traditional synchronous VLSI design requires that all computations in a logic stage complete in one clock cycle. Alternatively, by allowing computations in a logic stage to complete in a variable number of clock cycles, variable-latency design provides relaxed timing constraints for average performance, area and power consumption optimization. Proposed methodology involves signal probability based statistical timing analysis, determination of the logic computation latency, design of a prediction unit and a clock gating mechanism. In addition, I suggest an application-specific cross-layer analysis methodology. I further improve the methodology by addition of a timing-error detection mechanism to the prediction-based design. I present a performance variation model and propose a timing error rate estimation strategy based on statistical timing analysis. As opposed to detection and correction-based design paradigms which invoke considerable area and power overheads and face a number of circuit-level implementation problems, proposed prediction and detection-based variable-latency design methodology reduces the computation latency with relatively minimal cost. Concurrent checking or online monitoring methods are system-level techniques that conventionally incorporated for transient and intermittent fault detection. In the next part of the dissertation I present a hardware-based concurrent control-flow checking scheme for detection of software or hardware Trojan-based code injection attacks or dynamic integrity verification. I integrate a cipher-based hash-function in order to generate instruction sequence signature at runtime to protect against invalidation and circumvention attacks. In the final part of the dissertation, I propose and present a lightweight hardware-based Reconfigurable Reversible Computing (RRC) encryption/Decryption scheme. Suggested cryptography scheme achieve moving target defense and obfuscation through reconfigurability. One possible application of proposed scheme is the cipher-based hash function used in instruction sequence signature generation of proposed concurrent control-flow checking technique. Suggested scheme can be used as a standalone cryptographic module, or an addition to an existing scheme in order to mitigate side-channel attack treats. Furthermore, I present a Carbon Nanotube (CNT) crossbar-based nanoscale-computing platform as a more cost-effective alternative for secure implementation of cryptographic primitives. By incorporating CNT crossbar-based reconfigurable technology, minimal overhead to counteract supply chain, cryptanalysis and side-channel attacks is achieved. I compare suggested CNT-based reconfigurable reversible computing cryptographic scheme with FPGA and CMOS-based implementation of AES in hardware cost and attack complexity. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 119 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9781339718347 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/4350 | |
| dc.language | en | |
| dc.subject | Carbon Nanotube | |
| dc.subject | Cryptography | |
| dc.subject | Hardware Trojan | |
| dc.subject | Reliability | |
| dc.subject | Security | |
| dc.subject | Variable-latency Design | |
| dc.subject.classification | Electrical engineering | |
| dc.subject.classification | Computer engineering | |
| dc.subject.lcsh | Integrated circuits -- Very large scale integration -- Design and construction | |
| dc.subject.lcsh | Nanotechnology | |
| dc.subject.lcsh | Timing circuits | |
| dc.title | VLSI design for reliability and security in nanoscale technology | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Doctoral | |
| thesis.degree.name | Doctor of Philosophy |
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