Instruction Profiling Based Predictive Throttling for Power Optimization in Microprocessors
Power and performance have always been a critical trade-off in the designing of microprocessors. The emergence of portable devices has pushed the need for increased power efficiency without significant performance degradation and has made the power budget even more constrained. Technology scaling has long been the driving force for improving both power and performance. However, technology scaling alone cannot solve the power dissipation problem. Scaling increases power density per unit area which in turn reduces manufacturing yield. To make matters worse scaling has already reached or is reaching its limits. The problem of power efficiency has been intensely investigated and several techniques have been developed at the architecture, RTL (register transfer level), and circuit levels. Throttling is an architectural level solution that slows down the pipeline stages to reduce instant dynamic power. However, throttling achieves power savings at the expense of performance loss. Throttling is commonly applied at the fetch, issue, or at commit stage of a pipelined processor. Throttling is a technique that should be carefully implemented by identifying when, where and how long throttling should be applied for power optimization with minimal performance degradation. Throttling is still a critical problem in literature due to the dynamic workload of the processor. In designing pipeline, a balanced bandwidth of fetch, issue, and commit are maintained for execution to flow seamlessly. However, case studies have shown that bottleneck exists at different pipeline stages that result in performance degradation. The loss of performance indicates that there exists a proportional amount of wasted dynamic power due to pipeline flush. To address the wasted dynamic power, this thesis proposes instruction profiling based predictive throttling. Instruction profiling identifies a set of instructions that are causing a significant bottleneck in targeted processor architecture. Knowledge of the probable congestion for each instruction can enable efficient throttling mechanism. This study shows that instruction profiling based throttling at fetch and commit stages can save dynamic power with minimal performance loss. Additionally, the proposed throttling reduces wrong path execution that further improves effective energy consumption.