Design, implemantation and verification of high speed CMOS adders
| dc.contributor.advisor | John, Eugene | |
| dc.contributor.author | Talsania, Megha | |
| dc.contributor.committeeMember | Lin, Wei-Ming | |
| dc.contributor.committeeMember | Lee, Byeong Kil | |
| dc.date.accessioned | 2024-03-08T15:44:15Z | |
| dc.date.available | 2024-03-08T15:44:15Z | |
| dc.date.issued | 2013 | |
| dc.description | This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID. | |
| dc.description.abstract | All modern processors, including general purpose microprocessors, digital signal processors and Graphic Processing units contain an Arithmetic Logic Unit (ALU). The computing efficiency of modern processors mainly depends of the efficiency of the ALU. Modern ALUs can perform several complex functions including addition, multiplication and division. High speed adders are necessary in modern age. Special purpose processors, such as Digital Signal Processing chips use addition operation to increase the speed performance. In the past, the primary focus in the design of the adder was on circuit speed. However, low power requirement has become more and more important in recent years. The primary objective of this research is the design and realization of low power CMOS adders using 11 different algorithms. In this research mainly parallel prefix tree adders were analyzed. Also, several adder modules were analyzed to identify the optimal adder modules that can be used for the realization of the low power algorithm. The performance metrics considered for the analysis of the adders are: power, delay and area. In this research the CMOS adders were realized using TSMC 130nm, 90nm, 65nm and 40 nm technologies. For performance comparison, the adders were realized using various prefix tree algorithms. Using simulation studies, delay, area and power performance of the various adder modules were obtained. It was observed that Kogge stone Prefix tree adder has better circuit characteristics compared to adders realized using other algorithms. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 87 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9781303114557 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/5691 | |
| dc.language | en | |
| dc.subject | CMOS adders | |
| dc.subject | Delay calculation | |
| dc.subject | Functional Verification | |
| dc.subject | Low Power | |
| dc.subject | Prefix tree algorithm | |
| dc.subject | VLSI Design | |
| dc.subject.classification | Electrical engineering | |
| dc.title | Design, implemantation and verification of high speed CMOS adders | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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