Scheduling and layout techniques for thermal hotspot reduction in multi-core processors

The microprocessor performance has improved significantly over the years with advanced design techniques and with the enhanced scaling in CMOS technology. Among the design innovations that have helped gain the processor performance are the concepts of system-on-chip and multi-core processors. The new generation general purpose microprocessors are using multiple cores in the same chip in order to improve their performance. Each core in a multi-core processor chip is a microprocessor by itself. Having multiple cores allow for a microchip to run multiple processors independent of each other, or process in parallel. The greatest challenges that the multi-core technology is facing today are the high power dissipation and the smaller area footprints of the cores which cause high power densities that results in hotspots.

This dissertation focuses on reducing the thermal hotspots in multi-core processors. To this end two techniques are investigated in this research. These techniques are the thermal aware multi-core scheduling and the layout area expansion of selected high temperature components of the core. In the first technique the peak temperature reduction is achieved by migrating cores in underutilized multi-core processors. A thermal aware scheduling algorithm was developed to enable efficient scheduling of each core migration by identifying the most thermally suitable target core. The assessment of the core was made based on the real time temperature of the core which is under consideration and the temperatures and distances of other cores with respect to the core under consideration. Scheduling simulations were carried out using three simulators viz-a-viz Multi2Sim, McPAT, and Hotspots with SPEC 2006 benchmarks. The functional statistics and their power implications on Alpha microprocessor model are analyzed for the benchmark process. Thermal patterns in cores were studied as the migrations of the core occurred. A temperature reduction of 6°C was achieved with an average delay penalty of 2% of processing time. Additionally, an error estimation method based on the probability of the thermal coupling was developed and tested on simulation results in association with process to core ratio. Simulations carried out confirm that this scheduler shows optimal performance when process to core ratio is 22% or less.

The second technique investigated in this research to reduce hotspots in multi-core processors involves the trading of area for temperature reduction. By increasing the area footprint of small components of the microprocessor core with high power density, the peak temperature can be reduced. Hotspots simulator was used to analyze various components in the Alpha microprocessor. Based on the simulations, among the components that were having the highest temperatures, Return Broadcast Bus (RBB) was identified as a candidate for area trade-off for hotspot reduction. RBB is a very small area component compared to other components reaching high temperature, such as cache and Arithmetic Logic Unit. By increasing the area of Results Broadcast Bus, a temperature reduction of 3°C was achieved by increasing the area of RBB by 20% which is an area penalty of only 0.007% of the core area.

In contemporary computer networks, such as data centers, half of the power consumption is spent on cooling the microprocessors. Significant energy can be saved by abetting the peak temperature of microprocessors in addition to packaging and cooling hardware costs. Proposed techniques, the thermal aware multi-core scheduling and the layout area expansion, can be used to reduce the peak temperature with very little performance degradation while achieving large energy savings.